������: Xilinx
�a(ch��n)Ʒ�N�: CPLD - ��(f��)�s�ɾ���߉����
RoHS: Ԕ��(x��)��Ϣ
ϵ��: XC9536XL
���b�L(f��ng)��: SMD/SMT
���b / ���w: VQFP-64
�����Դ늉�: 3.3 V
��늳�?c��i)?sh��)��: 36
ݔ��/ݔ���˔�(sh��)��: 36 I/O
�Դ늉�-���: 3.6 V
�Դ늉�-��С: 3 V
��С�����ض�: 0 C
������ض�: + 70 C
������l��: 178 MHz
�������t�����ֵ: 7.5 ns
�̘�(bi��o): Xilinx
�惦(ch��)���: Flash
���������: Yes
�ŘO��(sh��)��: 800
߉��(sh��)�M�K��(sh��)������LAB: 2
�����Դ���: 10 mA
�a(ch��n)Ʒ���: CPLD - Complex Programmable Logic Devices
1
��e: Programmable Logic ICs
�����: 139.307 g
Features ? 5 ns pin-to-pin logic delays ? System frequency up to 178 MHz ? 36 macrocells with 800 usable gates ? Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (36 user I/O pins) - 64-pin VQFP (36 user I/O pins) - Pb-free available for all packages ? Optimized for high-performance 3.3V systems - Low power operation - 5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V signals - 3.3V or 2.5V output capability - Advanced 0.35 micron feature size CMOS Fast FLASH? technology ? Advanced system features - In-system programmable - Superior pin-locking and routability with Fast CONNECT? II switch matrix - Extra wide 54-input Function Blocks - Up to 90 product-terms per macrocell with individual product-term allocation - Local clock inversion with three global and one product-term clocks - Individual output enable per output pin - Input hysteresis on all user and boundary-scan pin inputs - Bus-hold circuitry on all user pin inputs - Full IEEE Standard 1149.1 boundary-scan (JTAG) ? Fast concurrent programming ? Slew rate control on individual outputs ? Enhanced data security features ? Excellent quality and reliability - Endurance exceeding 10,000 program/erase cycles - 20 year data retention - ESD protection exceeding 2,000V ? Pin-compatible with 5V-core XC9536 device in the 44-pin PLCC package and the 48-pin CSP package WARNING: Programming temperature range of TA = 0�� C to +70�� C